Partial metal grain size control to improve cmp loading effect

ABSTRACT

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a divisional application of U.S. patent applicationSer. No. 17/459,885, filed Aug. 27, 2021, the disclosure of which isincorporated by reference herein in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. In the course of IC evolution, functional density (i.e., thenumber of interconnected devices per chip area) has generally increasedwhile geometry size (i.e., the smallest component (or line) that can becreated using a fabrication process) has decreased. This scaling downprocess generally provides benefits by increasing production efficiencyand lowering associated costs. Such scaling down has also increased thecomplexity of processing and manufacturing ICs and, for these advancesto be realized, similar developments in IC processing and manufacturingare needed. As the dimensions of transistors decrease, the thickness ofthe gate oxide must be reduced to maintain performance with thedecreased gate length. However, in order to reduce gate leakage, highdielectric constant (high-k) gate dielectric layers are used which allowgreater physical thicknesses while maintaining the same effectivecapacitance as would be provided by a typical gate oxide used in largertechnology nodes. Additionally, as technology nodes shrink, in some ICdesigns, there has been a desire to replace the typically polysilicongate electrode with a metal gate electrode to improve device performancewith the decreased feature sizes. In some instances, metal gates aremanufactured using a replacement metal gate process.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flowchart illustrating a method for fabricating asemiconductor structure, in accordance with some embodiments.

FIGS. 2A-2I are cross-sectional views of a first exemplary semiconductorstructure at various fabrication stages of the method of FIG. 1 , inaccordance with some embodiments.

FIGS. 3A and 3B are cross-sectional views of a second exemplarysemiconductor structure obtained using the method of FIG. 1 , inaccordance with some embodiments.

FIG. 4 is a flowchart illustrating a method for fabricating asemiconductor structure, in accordance with some embodiments.

FIGS. 5A-5F are cross-sectional views of a first exemplary semiconductorstructure at various fabrication stages of the method of FIG. 4 , inaccordance with some embodiments.

FIGS. 6A and 6B are cross-sectional views of a second exemplarysemiconductor structure obtained using the method of FIG. 4 , inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

In the gate-last approach, metals are often used to form the gateelectrodes of the transistors. The formation of the metal gates mayinclude forming sacrificial gate electrodes, and then removing thesacrificial gate electrodes to form gate cavities. A suitable conductivemetal is then filled into the gate cavities, followed by chemicalmechanical polishing (CMP) to remove the excess portions of theconductive metal. The remaining portions of the conductive metal left inthe gate cavities form replacement gates for the respective transistors.

Semiconductor ICs include devices such as transistors, capacitors,resistors, and inductors that are formed in or on the substrate of an ICusing lithography and patterning techniques. These semiconductor devicesare inter-connected according to the design of the IC to implementdifferent functions. In a typical IC, the silicon area is divided intomany regions for different functions. The difference in pattern densityof different regions may cause an undesirable loading in the gate metalCMP process. As the polishing rate in a low pattern density region ishigher than the polishing rate in a high pattern density region, the lowpattern density region exhibits a severe dishing effect. This CMP loadeffect causes gate height variation in different regions, which inducesdevice mismatch.

In embodiments of the present disclosure, prior to the CMP process, themetal layer for formation of metal gates is doped in selected regions toreduce the metal grain size, which in turn leads to increase in themetal polishing rate in the selected regions. The selectively doping ofthe metal layer helps to reduce the CMP loading effect caused by thedifference in polishing rates of a metal film from one location toanother. As a result, more uniform gate heights can be achieved acrossall regions of the IC chips.

FIG. 1 is a flowchart of a method 100 for fabricating a semiconductorstructure 200, in accordance with various aspects of the presentdisclosure. FIGS. 2A-2I are cross-sectional views of the semiconductorstructure 200 in various stages of a manufacturing process, inaccordance with some embodiments. The method 100 is discussed in detailbelow, with reference to the semiconductor structure 200, in FIGS.2A-2I. In some embodiments, additional operations are performed before,during, and/or after the method 100, or some of the operations describedare replaced, and/or eliminated. In some embodiments, additionalfeatures are added to the semiconductor structure 200. In someembodiments, some of the features described below are replaced oreliminated. One of ordinary skill in the art would understand thatalthough some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

In some embodiments, embodiments such as those described herein relateto fin field effect transistors (FinFETs). A FinFET refers to anyfin-based, multi-gate transistor. In some alternative embodiments,embodiments such as those described herein relate to planar field effecttransistors (FETs).

At operation 102, the method 100 (FIG. 1 ) forms a plurality of firstsacrificial gate structures 210A over a first active region 202A in alarge array region 202L of a substrate 202 and a plurality of secondsacrificial gate structures 210B over a second active region 202B in asmall array region 202S of the substrate 202. FIG. 2A is across-sectional view of the semiconductor structure 200 after formingthe plurality of first sacrificial gate structures 210A over the firstactive region 202A in the large array region 202L of the substrate 202and the plurality of second sacrificial gate structures 210B over thesecond active region 202B in the small array region 202S of thesubstrate 202, in accordance with some embodiments.

Referring to FIG. 2A, the substrate 202 is provided. In someembodiments, the substrate 202 is a bulk semiconductor substrate. A“bulk” semiconductor substrate refers to a substrate that is entirelycomposed of at least one semiconductor material. In some embodiments,the bulk semiconductor substrate includes a semiconductor material or astack of semiconductor materials such as, for example, silicon (Si),germanium (Ge), silicon germanium (SiGe), carbon doped silicon (Si:C),silicon germanium carbon (SiGeC); or an III-V compound semiconductorsuch as, for example, gallium arsenide (GaAs), gallium phosphide (GaP),indium phosphide (InP), indium arsenide (InAs), indium antimonide(InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide(AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide(GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenidephosphide (GaInAsP). In some embodiments, the bulk semiconductorsubstrate includes a single crystalline semiconductor material such as,for example, single crystalline silicon. In some embodiments, the bulksemiconductor substrate is doped depending on design requirements. Insome embodiments, the bulk semiconductor substrate is doped with p-typedopants or n-type dopants. The term “p-type” refers to the addition ofimpurities to an intrinsic semiconductor that creates deficiencies ofvalence electrons. Exemplary p-type dopants, i.e., p-type impurities,include, but are not limited to, boron, aluminum, gallium, and indium.“N-type” refers to the addition of impurities that contribute freeelectrons to an intrinsic semiconductor. Exemplary n-type dopants, i.e.,n-type impurities, include, but are not limited to, antimony, arsenic,and phosphorous. If doped, the substrate 202, in some embodiments, has adopant concentration in a range from 1.0×10¹⁴ atoms/cm³ to 1.0×10¹⁷atoms/cm³, although the dopant concentrations may be greater or smaller.In some embodiments, the substrate 202 is a semiconductor-on-insulator(SOI) substrate including a top semiconductor layer formed on aninsulator layer (not shown). The top semiconductor layer includes theabove-mentioned semiconductor material such as, for example, Si, Ge,SiGe, Si:C, SiGeC; or an III-V compound semiconductor including GaAs,GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInASP.The insulator layer is, for example, a silicon oxide layer, or the like.The insulator layer is provided over a base substrate, typically asilicon or glass substrate.

The substrate 202 includes a large array region 202L and a small arrayregion 202S. The large array region 202L and the small array region 202Smay or may not be contiguous and any number of device features (e.g.,isolation regions, dummy features, or the like, not shown) may be formedbetween the large array region 202L and the small array region 202Sdepending on device design. The large array region 202L occupies arelatively large area of the substrate 202 compared to the area occupiedby the small array region 202S. The large array region 202L is a lowpattern density region, while the small array region 202S is a highpattern density region. In some embodiments, the density of the devicesto be formed in the large array region 202L is equal to or greater than40K devices/μm². In some embodiments, the density of the devices to beformed in the small array region 202S is less than 300K devices/μm². Insome embodiments, less than 100K gate structures may be formed in thesmall array region 202S.

Isolation structures 204 are formed in the substrate 202 to definevarious active regions, e.g., a first active region 202A in the largearray region 202L and a second active region 202B in the small arrayregion 202S. In some embodiments, the active regions 202A, 202B areplanar structures formed in an upper portion of the substrate 202 forformation of planar FETs. In some other embodiments, the active regions202A, 202B are three-dimension (3D) structures, such as fins, forformation of FinFETs. In some embodiments, the fins are formed bylithography and etching. In some embodiments, a photoresist layer isapplied on substrate 202 and patterned to provide a patternedphotoresist layer atop the substrate 202. The pattern in the patternedphotoresist layer is then transferred into the substrate 202 by ananisotropic etch to provide fins. In some embodiments, the etchingprocess used for pattern transfer includes a dry etch such as, forexample, reactive ion etch (RIE), plasma etch, ion beam etch or laserablation. After transferring the pattern into the substrate 202, thepatterned photoresist layer is removed utilizing a resist strippingprocess such as, for example, ashing. In some embodiments, other methodssuch as sidewall image transfer (SIT) or directional self-assembly (DSA)are used to form fins. In still some other embodiments, the activeregions 202A, 202B are nanosheets, such as nanowires, for formation ofnanowire FETs.

In some embodiments, the isolation structures 204 are shallow trenchisolation (STI) structures. Formation of the isolation structures 204includes etching trenches in the substrate 202 and filling the trencheswith one or more insulator materials such as silicon dioxide, siliconnitride, or silicon oxynitride. In some embodiments, one or moreisolation structures 204 have a multi-layer structure including athermal oxide liner and silicon nitride filling the trench. In someembodiments, trenches are formed by applying a photoresist layer on thesubstrate 202, lithographically patterning the photoresist layer, andtransferring the pattern in the photoresist layer into an upper portionof the substrate 202 using an anisotropic etch such as RIE or plasmaetch. Insulator materials are then deposited to fill the trenches using,for example, chemical vapor deposition (CVD), physical vapor deposition(PVD), or atomic layer deposition (ALD). Next, a CMP process isperformed to polish back excessive insulator materials and planarize topsurfaces of the isolation structures 204. In some embodiments, theisolation structures 204 are formed by oxidizing or nitriding portionsof substrate 202. In some embodiments, the isolations structures 204have top surfaces coplanar with the top surfaces of the active regions202A, 202B. In instances where the active regions 202A, 202B are fins,the insulator materials are etched back to physically expose upperportions of the semiconductor fins. In some embodiments, a wet etchemploying an etching chemical such as, for example, dilute hydrofluoricacid, may be used to etch the insulator materials. Accordingly, theisolation structures 204 surround bottom portions of semiconductor fins.

The first sacrificial gate structures 210A are formed over the firstactive region 202A and the second sacrificial gate structures 210B areformed over the second active region 202B. Each of the first and secondsacrificial gate structures 210A, 210B includes a sacrificial gate stack(212, 214) over a portion of a corresponding active region 202A or 202Band gate spacers 216 on sidewalls of the sacrificial gate stack (212,214). In instances where the active region 202A or 202B is a planaractive region, each sacrificial gate structure 210A, 210B is formed atopthe corresponding active region 202A, 202B. In instances where theactive region 202A or 202B has a fin structure, each sacrificial gatestructure 210A, 210B straddles a portion of a corresponding activeregion 202A or 202B such that the sacrificial gate structure 210A, 210Bis formed atop and along sidewalls of a corresponding active region202A, 202B. The term “sacrificial gate stack” as used herein refers to aplaceholder structure for a subsequently formed functional gate stack.The term “functional gate stack” as used herein refers to a permanentgate stack used to control output current (i.e., flow of carriers in thechannel) of a semiconducting device through electrical fields ormagnetic fields.

The sacrificial gate stack (212, 214) includes, from bottom to top, asacrificial gate dielectric 212 and a sacrificial gate conductor 214. Insome embodiments, the sacrificial gate stack (212, 214) may also includea sacrificial gate cap (not shown) over the sacrificial gate conductor.In some embodiments, the sacrificial gate dielectric 212 is omitted. Insome embodiments, the sacrificial gate stack (212, 214) is formed byproviding a sacrificial material stack (not shown) that includes, frombottom to top, a sacrificial gate dielectric layer and a sacrificialgate conductor layer over the first active region 202A and the secondactive region 202B, and then patterning the sacrificial material stack.

In some embodiments, the sacrificial gate dielectric layer includessilicon oxide, silicon nitride, or silicon oxynitride. In someembodiments, the sacrificial gate dielectric layer is formed utilizing adeposition process such as, for example, CVD or PVD. In someembodiments, the sacrificial gate dielectric layer is formed byconversion of a surface portion of the first active region 202A and thesecond active region 202B utilizing thermal oxidation or nitridation.

In some embodiments, the sacrificial gate conductor layer includespolysilicon. In some embodiments, the sacrificial gate conductor layeris formed utilizing a deposition process such as, for example, CVD orPECVD.

In some embodiments, the sacrificial gate material stack is patterned bylithography and etching. For example, a photoresist layer is appliedover the topmost surface of the sacrificial material stack andlithographically patterned by lithographic exposure and development. Thepattern in the photoresist layer is sequentially transferred into thesacrificial material stack by at least one anisotropic etch. Theanisotropic etch is a dry etch, for example RIE, a wet etch, or acombination thereof. If not completely consumed, the remainingphotoresist layer after formation of the sacrificial gate stack isremoved by, for example, ashing.

In some embodiments, the gate spacers 216 include a dielectric materialsuch as, for example, an oxide, a nitride, an oxynitride, orcombinations thereof. In some embodiments, the gate spacers 216 comprisesilicon nitride. In some embodiments, the gate spacers 216 are formed byfirst depositing a conformal gate spacer material layer on exposedsurfaces of the sacrificial gate stack (212, 214), the first and secondactive regions 202A, 202B, and the isolation structures 204 and thenetching the gate spacer material layer to remove horizontal portions ofthe gate spacer material layer. In some embodiments, the gate spacermaterial layer is deposited, for example, by CVD, PECVD, or atomic layerdeposition (ALD). In some embodiments, the gate spacer material layer isetched by dry etch such as, for example, RIE. Remaining verticalportions of the gate spacer material layer on the sidewalls ofsacrificial gate stacks (212, 214) constitute the gate spacers 216.

At operation 104, the method 100 (FIG. 1 ) forms first source/drainstructures 218A on opposite sides of the first sacrificial gatestructures 210A and second source/drain structures 218B on oppositesides of the second sacrificial gate structures 210B. FIG. 2B is across-sectional view of the semiconductor structure 200 of FIG. 2A afterforming the first source/drain structures 218A on the opposite sides ofthe first sacrificial gate structures 210A and the second source/drainstructures 218B on the opposite sides of the second sacrificial gatestructures 210B, in accordance with some embodiments.

Referring to FIG. 2B, the first source/drain structures 218A are formedin portions of the first active region 202A that are not covered by thefirst sacrificial gate structures 210A and the second source/drainstructures 218B are formed in portions of the second active region 202Bthat are not covered by the second sacrificial gate structure 210B.Here, a source/drain structure functions as either a source or a drainfor a FET depending on the wiring of the FET.

In some embodiments, the source/drain structures 218A, 218B are dopedsemiconductor structures. In some embodiments, the source/drainstructures 218A, 218B independently include a semiconductor materialsuch as, for example, Si, SiGe, Si:C, Ge, or an III-V material such asGaAs, InP, GaP, or GaN. The source/drain structures 218A, 218B containsdopants of appropriate conductivity types. For example, in someembodiments, the first source/drain structures 218A may contain n-typedopants for formation of n-type transistors, while the secondsource/drain structures 218B may contain p-type dopants for formation ofp-type transistors, and vice versa. The dopant concentration in thesource/drain structures 218A, 218B can be from about 1×10¹⁹ atoms/cm³ toabout 2×10²¹ atoms/cm³, although lesser or greater dopant concentrationsare also contemplated.

In some embodiments, the source/drain structures 218A, 218B areepitaxial layers formed by one or more selective epitaxial growthprocesses. During a selective epitaxial growth, the depositedsemiconductor material grows only on exposed semiconductor surfaces,such as surfaces of the active regions 202A, 202B, but does not grow ondielectric surfaces, such as the surfaces of the isolation structures204 and the gate spacers 216. In some embodiments, when the activeregions 202A, 202B are fins, the deposited semiconductor material growson sidewalls and top surfaces of the semiconductor fins. In someembodiments, the source/drain structures 218A, 218B are formed bymolecular beam epitaxy (MBE).

In some embodiments, the source/drain structures 218A, 218B are in-situdoped with dopants of appropriate conductivity type, n-type or p-type,during the epitaxial growth processes. In some embodiments, thesource/drain structures 218A, 218B are doped (ex-situ) after theepitaxial growth process utilizing, for example, ion implantation. Forexample, to form n-type transistors in the first active region 202A,n-type dopants such as phosphorus or arsenic are implanted into thedeposited semiconductor material on the first active region 202A, whilethe second active region 202B is covered by a mask. Similarly, to formp-type transistors in the second active region 202B, p-type dopants suchas boron or BF 2 are implanted into the deposited semiconductor materialon the second active region 202B, while the first active region 202A iscovered by a mask.

Alternatively, in some embodiments, the source/drain structures 218A,218B are formed by implanting dopants of appropriate types into theportions of corresponding active regions 202A, 202B not covered by thesacrificial gate structures 210A, 210B.

In some embodiments, the source/drain structures 218A, 218B are furtherexposed to an annealing process to activate the dopants in thesource/drain structures 218A, 218B after forming the source/drainstructures 218A, 218B and/or after the subsequent doping process. Insome embodiments, the dopants in the source/drain structures 218A, 218Bare activated by a thermal annealing process including a rapid thermalannealing process, a laser annealing process, or a furnace annealingprocess. In some embodiments, the dopants in the epitaxy source/drainstructures 218A, 218B are diffused into the underlying correspondingactive regions 202A, 202B to dope surface portions of the correspondingactive regions 202A, 202B.

At operation 106, the method 100 (FIG. 1 ) deposits an interleveldielectric (ILD) layer 220 over the substrate 202. FIG. 2C is across-sectional view of the semiconductor structure 200 of FIG. 2B afterdepositing the ILD layer 220 over the substrate 202, in accordance withsome embodiments.

Referring to FIG. 2C, the ILD layer 220 is deposited over the substrate202 to fill the spaces between the sacrificial gate structures 210A,210B. In some embodiments, the ILD layer 220 includes silicon oxide.Alternatively, in some embodiments, the ILD layer 220 includes a low-kdielectric material having a dielectric constant (k) less than siliconoxide. In some embodiments, the low-k dielectric material has adielectric constant from about 1.2 to about 3.5. In some embodiments,the ILD layer 220 includes silicon oxide made fromtetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or dopedsilicate glass such as borophosphosilicate glass (BPSG), fluorosilicaglass (FSG), phosphosilicate glass (PSG), boron doped silicon glass(BSG), and/or other suitable dielectric materials. In some embodiments,the ILD layer 220 is deposited by CVD, PECVD, PVD, or spin coating. Insome embodiments, the ILD layer 220 is deposited to have a top surfaceabove the topmost surface of the sacrificial gate structure 210A, 210B(e.g., the top surface of the sacrificial gate conductor 214). The ILDlayer 220 is subsequently planarized, for example, by CMP. After theplanarization, the ILD layer 220 has a surface coplanar with the topmostsurface of the sacrificial gate structure 210A, 210B.

At operation 108, the method 100 (FIG. 1 ) removes the sacrificial gatestacks (212, 214) from respective gate structures 210A, 210B to providea plurality of first gate cavities 224 in the large array region 202Land a plurality of second gate cavities 226 in the small array region202S. FIG. 2D is a cross-sectional view of the semiconductor structure200 of FIG. 2C after removing the sacrificial gate stacks (212, 214)from respective gate structures 210A, 210B to provide the plurality offirst gate cavities 224 in the large array region 202L and the pluralityof second gate cavities 226 in the small array region 202S, inaccordance with some embodiments.

Referring to FIG. 2D, various components of the sacrificial gate stack(212, 214) are removed selectively to the semiconductor materials thatprovide the active regions 202A, 202B and the dielectric materials thatprovide the gate spacers 216 and the ILD layer 220 by at least one etch.In some embodiments, the at least one etch is a dry etch such as RIE, awet etch such as an ammonia etch, or a combination thereof. Each gatecavity 224, 226 occupies a volume from which the correspondingsacrificial gate stack (212, 214) is removed and is laterally confinedby inner sidewalls of the corresponding gate spacers 216. After removalof the sacrificial gate stacks (212, 214), the active regions 202A, 202Bare physically exposed by the corresponding gate cavities 224, 226.

At operation 110, the method 100 (FIG. 1 ) deposits a high-k dielectriclayer 234 along sidewalls and bottom surfaces of the gate cavities 224,226 and over the ILD layer 220 followed by depositing a gate electrodelayer 236 over the high k-dielectric layer 234. FIG. 2E is across-sectional view of the semiconductor structure 200 of FIG. 2D afterdepositing the high-k dielectric layer 234 along the sidewalls and thebottom surfaces of the cavities 224, 226 and over the ILD layer 220 andthen depositing the gate electrode layer 236 over the high k-dielectriclayer 234, in accordance with some embodiments.

Referring to FIG. 2E, the high-k dielectric layer 234 is deposited overthe sidewalls and bottom surfaces of the gate cavities 224, 226 and thetop surface of the ILD layer 220. In some embodiments, the high-kdielectric layer 234 includes a high-k dielectric material having adielectric constant greater than silicon oxide. Exemplary high-kdielectric materials include, but are not limited to, silicon nitride(Si₃N₄), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), lanthanum oxide(La₂O₃), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), strontiumtitanium oxide (SrTiO₃), lanthanum Aluminum oxide (LaAlO₃), yttriumoxide (Y₂O₃), and combinations thereof. In some embodiments, the high-kdielectric layer 234 is deposited as a conformal layer using a suitabledeposition process including, for example, CVD, PECVD, PVD, or ALD.

In some embodiments, prior to depositing the high-k dielectric layer234, an interfacial dielectric 232 is formed on the bottom surface ofeach of gate cavities 224, 226. In some embodiments, the interfacialdielectric 232 includes a dielectric oxide such as silicon oxide. Insome embodiments, the interfacial dielectric 232 is formed thermal orchemical oxidization of a surface portion of an active region 202A, 202Bthat is exposed by a corresponding gate cavities 224, 226. In someembodiments, the chemical oxidation involves using a chemical oxidantsuch as, ozone, hydrogen peroxide, or the like. In some otherembodiments, the interfacial dielectric 232 is formed by ALD, CVD orother suitable methods. The interfacial dielectric 232 is optional andcan be omitted in some embodiments.

The gate electrode layer 236 is deposited over the high-k dielectriclayer 234 to fill the remaining volume of each of gate cavities 224,226. In some embodiments, the gate electrode layer 236 includes aconductive metal such as, for example, tungsten (W), copper (Cu),aluminum (Al), cobalt (Co), titanium (Ti), tantalum (Ta), molybdenum(Mo), ruthenium (Ru), platinum (Pt), iridium (Jr), a silicide thereofsuch as ZrSi₂, TaSix, MoSix, NiSix, PtSi, or PtSi, a nitride thereofsuch as HfN, TiN, TaN or MoN, or an alloy thereof. In some embodiments,the gate electrode layer 236 is deposited by CVD, PVD, plating, and/orother suitable processes.

At operation 112, the method 100 (FIG. 1 ) implants dopants into atleast a portion of the gate electrode layer 236 in the small arrayregion 202S. In some embodiments, an entire portion of the gateelectrode layer 236 in the small array region 202S is doped (FIG. 2F).FIG. 2F is a cross-sectional view of the semiconductor structure 200 ofFIG. 2E after implanting the dopants into the entire portion of the gateelectrode layer 236 in the small array region 202S, in accordance withsome embodiments. In other embodiments, only an upper portion of thegate electrode layer 236 in the small array region 202S is doped. FIG.2G is a cross-sectional view of the semiconductor structure 200 of FIG.2E after implanting the dopants into the upper portion of the gateelectrode layer 236 in the small array region 202S, in accordance withsome other embodiments.

Referring to FIGS. 2F and 2G, a patterned photoresist layer 240 isformed to mask a portion of the gate electrode layer 236 in the largearray region 202L, while exposing a portion of the gate electrode layer236 in the small array region 202S. In some embodiments, the patternedphotoresist layer 240 is formed by first applying a photoresist layerover the gate electrode layer 236, exposing the photoresist layer toradiation through a photomask, and followed by etching away an exposedor unexposed region using a developer.

Subsequently, an ion implantation 250 is performed to introduce dopantsinto the portion of the gate electrode layer 236 in the small arrayregion 202S that is exposed by the patterned photoresist layer 240,thereby forming a doped metal portion 236B in the gate electrode layer236. In some embodiments, the ion implantation 250 can be performed byimplanting dopant species including, but not limited to, carbon (C),silicon (Si), germanium (Ge) tin (Sn), a noble gas such as helium (He),Neon (Ne), argon (Ar), krypton (Kr) or xenon (Xe), or a mixture thereof,into the exposed portion of the gate electrode layer 236. Depending onthe thickness of the gate electrode layer 236 and the dopant speciesused, the implant dosage can range from 1×10¹² dopants/cm² to 5×10¹⁵dopants/cm², and the implant energy can range from 10 KeV to 150 KeV.One or more implant parameters such as implant dosage, implant energyand implant time may be adjusted to control the depth of the ionimplantation. In some embodiments, and as in FIG. 2F, the one or moreimplant parameters are controlled such that the gate electrode layer 236in the small array region 202S is doped through its entire thickness.That is, an entire portion of the gate electrode layer 236 within eachgate cavity 226 in the small array region 202S is doped. In some otherembodiments and as in FIG. 2G, the one or more implant parameters arecontrolled such that only an upper portion of the gate electrode layer236 in the small array region 202S is doped with dopants. That is, anupper portion of the gate electrode layer 236 within each gate cavity226 in the small array region 202S is doped. The undoped portion of thegate electrode layer 236 is herein referred to as an undoped metalportion 236A. The introduction of dopants reduces the gain size of metalin the doped metal portion 236B. As a result, the grain size of metal inthe doped metal portion 236B is smaller than the grain size of metal inthe undoped metal portion 236A. In some embodiments, the grain size ofmetal in the undoped metal portion 236A is in a range from about 0.5 μmto about 75 μm, and the grain size of metal in the doped metal portion236B is in a range from about 0.01 μm to about 0.5 μm.

The ion implantation 250 also dopes at least a portion of the ILD layer220 in the small array region 202S with the dopants. In someembodiments, and as in FIG. 2F, an entire portion of the ILD layer 220in the small array region 202S is doped. In some other embodiments, andas in FIG. 2G, only an upper portion of the ILD layer 220 in the smallarray region 202S is doped. The doped portion of the ILD layer 220 isherein referred to as a doped ILD portion 220B.

In some embodiments, after dopant species are implanted into the exposedportion of the gate electrode layer 236 in the small array region 202S,the semiconductor structure 200 may be annealed. Such an anneal processcan drive the dopants further into the gate electrode layer 236 towardsthe substrate 202. In some embodiments, the dopants in the doped metalportion 236B may be uniformly distributed throughout the entirethickness. In some embodiments, the dopants in the doped metal portion236B may have a gradient dopant profile with the dopant concentrationbeing the least at the bottom of the doped metal portion 236B proximateto the substrate 202.

After the ion implantation, the patterned photoresist layer 240 isremoved by, for example, ashing.

At operation 114, the method 100 (FIG. 1 ) removes excess portions ofthe gate electrode layer 236 and the high-k dielectric layer 234 outsidethe gate cavities 224, 226 to form a plurality of first gate structures260A in the large array region 202L and a plurality of second gatestructures 260B in the small array region 202S. FIG. 2H is across-sectional view of the semiconductor structure 200 of FIG. 2F afterremoving the excess portions of the gate electrode layer 236 and thehigh-k dielectric layer 234 outside the gate cavities 224, 226 to formthe plurality of first gate structures 260A in the large array region202L and the plurality of second gate structures 260B in the small arrayregion 202S, in accordance with some embodiments. FIG. 2I is across-sectional view of the semiconductor structure 200 of FIG. 2G afterremoving the excess portions of the gate electrode layer 236 and thehigh-k dielectric layer 234 outside the gate cavities 224, 226 to formthe plurality of first gate structures 260A in the large array region202L and the plurality of second gate structures 260B in the small arrayregion 202S, in accordance with alternative embodiments.

Referring to FIGS. 2H and 2I, the first gate structures 260A are formedin the large array region 202L of the substrate 202. Each of the firstgate structures 260A includes a first gate stack and gate spacers 216surrounding the first gate stack. In some embodiments, each first gatestack includes an interfacial dielectric 232, a high-k gate dielectric234P, and a first gate electrode 236F. The second gate structures 260Bare formed in the small array region 202S of the substrate 202. Each ofthe second gate structures 260B includes a second gate stack and gatespacers 216 surrounding the second gate stack. In some embodiments, eachsecond gate stack includes an interfacial dielectric 232, a high-k gatedielectric 234P, and a second gate electrode 236S.

The first and second gate structures 260A, 260B can be formed by aplanarization process, such as CMP, which removes excess portions of thegate electrode layer 236 and the high-k dielectric layer 234 disposedover the top surface of the ILD layer 220. The CMP process may stop whenreaching the ILD layer 220. A remaining portion of the high-k dielectriclayer 234 within each of first and second gate cavities 224, 226constitutes the high-k gate dielectric 234P. A remaining portion of thegate electrode layer 236 within each first gate cavity 224 constitutesthe first gate electrode 236F. The first gate electrode 236F is formedwith the undoped metal portion 236A. A remaining portion of the gateelectrode layer 236 within each second gate cavity 226 constitutes thesecond gate electrode 236S. At least a portion of the second gateelectrode 236S is made with a doped metal portion 236B. In instanceswhere the entire portion of the gate electrode layer 236 in the smallarray region 202S is doped, after the planarization, an entirety of thesecond gate electrode 236S is formed with the doped metal portion 236B(FIG. 2H). In instances where only the upper portion of the gateelectrode layer 236 in the small array region 202S is doped, after theplanarization, the second gate electrode 236S has a bilayer structureincluding an undoped metal portion 236A and a doped metal portion 236Boverlying the undoped metal portion 236A.

The CMP process exhibits a higher polishing rate for small grain sizemetal than large grain size metal. As a result, the doped metal portion236B in the small array region 202S can be polished faster than theundoped metal portion 236A in the large array region 202L. Throughcontrol of local metal grain sizes which allows control of polishingrates in respective large array region 202L and small array region 202S,the metal gate CMP loading effect is reduced, and the gate heightuniformity across the substrate 202 is improved.

FIGS. 3A and 3B are cross-sectional views of a semiconductor structure300 that can be formed by performing the method 100 of FIG. 1 , inaccordance with some embodiments. Components in the semiconductorstructure 300 that are the same or similar to the semiconductorstructure 200 are given the same references numbers, and detaileddescription thereof is thus omitted.

Unlike the semiconductor structure 200 in which the dopants are onlyimplanted into a portion of the gate electrode layer 236 in the smallarray region 202S, in the semiconductor structure 300, dopants are alsointroduced into a portion of the gate electrode layer 236 in theperipheral portion of the large array region 202L. As a result, thefirst gate structures 260A formed in the large array region 202Lincludes a pair of outer first gate structures 260A′ near the edges ofthe series of the first gate structures 260A and inner first gatestructures 260A″ between the outer first gate structures 260A′. Thefirst gate electrode 236F in each of outer first gate structures 260A′at the peripheral region of the large array region 202L is formed withthe doped metal portion 236B, while the first gate electrode 236F ineach of the inner first gate structures 260A″ between the outer firstgate structures 260′ is formed with the undoped metal portion 236A. Insome embodiments, and as in FIG. 3A, an entirety of the first gateelectrode 236F in each of the outer first gate structures 260A′ isformed with a doped metal portion 236B. In some embodiments, and as inFIG. 3B, only an upper portion of the first gate electrode 236F in eachof the outer first gate structures 260A′ is formed with a doped metalportion 236B. The first gate electrode 236F in each of the outer firstgate structures 260A′ thus has a bilayer structure including an undopedmetal portion 236A and a doped metal portion 236B atop of the undopedmetal portion 236A.

During the CMP of the gate electrode layer 236, selectively doping themetal in the portion of the gate electrode layer 236 in the outer gatestructure region reduces the metal grains size, which leads to increasein the metal removal rate in the outer first gate structure region. As aresult, the gate height uniformity of the resulting inner and outerfirst gate structures 260A′, 260A″ in the large array region 202L isimproved, which in turn leads to improved device performance.

FIGS. 2A-2I, 3A and 3B illustrate formation of metal gate structureswith improved gate height uniformity using selective ion implantation tochange grain size of the metal, which allows for control of metalpolishing rates at regions of different pattern densities. The selectiveion implantation can also be used to improve the contact heightuniformity for contact structures in the back end of line (BEOL)processing.

FIG. 4 is a flowchart of a method 400 of fabricating a semiconductorstructure 500, in accordance with various aspects of the presentdisclosure. FIGS. 5A-5G are cross-sectional views of the semiconductorstructure 500 in various stages of a manufacturing process, inaccordance with some embodiments. The method 400 is discussed in detailbelow, with reference to the semiconductor structure 500, in FIGS.5A-5G. In some embodiments, additional operations are performed before,during, and/or after the method 400, or some of the operations describedare replaced, and/or eliminated. In some embodiments, additionalfeatures are added to the semiconductor structure 500. In someembodiments, some of the features described below are replaced oreliminated. One of ordinary skill in the art would understand thatalthough some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

At operation 402, the method 400 (FIG. 4 ) etches a contact leveldielectric layer 510 disposed over a substrate 502 to form a pluralityof contact openings 512, 514. FIG. 5A is a cross-sectional view of thesemiconductor structure 500 after etching the contact level dielectriclayer 510 disposed over the substrate 502 to form the plurality ofcontact openings 512, 514.

Referring to FIG. 5A, the substrate 502 includes a large array region502L and a small array region 502S containing devices of differentdensities. The large array region 502L and the small array region 502Smay or may not be contiguous and any number of device features (e.g.,isolation regions, dummy features, or the like, not shown) may be formedbetween the large array region 502L and the small array region 502Sdepending on device design. The large array region 502L occupies arelatively large area of the substrate 502 compared to the area occupiedby the small array region 502S. The large array region 502L is a lowpattern density region, while the small array region 502S is a highpattern density region. In some embodiments, the substrate 502 includesactive devices such as p-type field effect transistors (PFETs), n-typefield effect transistors (NFETs), metal-oxide semiconductor (MOS)transistors, complementary metal-oxide semiconductor (CMOS) transistors,bipolar transistors, high voltage transistors, and/or high frequencytransistors. In some embodiments, the transistors are planar transistorsor 3D fin field effect transistors (FinFETs). In some embodiments, thesubstrate 502 further includes passive devices such as resistors,capacitors, and/or inductors. The substrate 502 further includesisolation structures such as STI structures to separate various activeand/or passive devices from one another. For convenience, any suchcircuit elements are not shown in FIG. 5A.

The contact level dielectric layer 510 is deposited over the substrate502. In some embodiments, and as in FIG. 5A, the contact leveldielectric layer 510 is deposited directly above and in contact with thesubstrate 502. In some embodiments, one or more dielectric layerscontaining contact/interconnect structures therein are disposed betweenthe contact level dielectric layer 510 and the substrate 502.

In some embodiments, the contact level dielectric layer 510 includessilicon oxide. Alternatively, in some embodiments, the contact leveldielectric layer 510 includes a low-k dielectric material having adielectric constant (k) less than silicon oxide. In some embodiments,the low-k dielectric material has a dielectric constant from about 1.2to about 3.5. In some embodiments, the contact level dielectric layer510 includes silicon oxide made from TEOS oxide, undoped silicate glass,or doped silicate glass such as borophosphosilicate glass, fluorosilicaglass, phosphosilicate glass, boron doped silicon glass, and/or othersuitable dielectric materials. In some embodiments, the contact leveldielectric layer 510 is deposited by CVD, PECVD, PVD, or spin coating.In some embodiments, the contact level dielectric layer 510 isplanarized by a planarization process or otherwise recessed to provide aplanar top surface. In some embodiments, the surface of the contactlevel dielectric layer 510 is planarized using a CMP process.

The contact level dielectric layer 510 is subsequently etched to formthe plurality of contact openings 512, 514 therein. In some embodiments,the contact openings 512, 514 are trenches or combinations of a trenchand a via. The plurality of contact opening includes a plurality offirst contact openings 512 formed in the large array region 502L of thesubstrate 502 and a plurality of second contact openings 514 formed inthe small array region 502S of the substrate 502.

The contact level dielectric layer 510 is etched with lithography andetching processes. In some embodiments, the lithography process includesapplying a photoresist layer (not shown) over the contact leveldielectric layer 510, exposing the photoresist layer to a pattern,performing post-exposure baking, and developing the resist to form apatterned photoresist layer (not shown). The patterned photoresist layerexposes portions of the contact level dielectric layer 510 where thecontact openings 512, 514 are to be formed. Next, the portions of thecontact level dielectric layer 510 exposed by the patterned photoresistlayer are etched to form the contact openings 512, 514. In someembodiments, the contact level dielectric layer 510 is etched using adry etch such as, for example, a reactive ion etch (RIE) or a plasmaetch. In some embodiments, the contact level dielectric layer 510 isetched using a wet etch. After formation of the contact openings 512,514 in the contact level dielectric layer 510, the patterned photoresistlayer is removed, for example, by ashing. Alternatively, in someembodiments, a hard mask is used such that the contact opening patternis transferred from the pattered photoresist layer to the hard mask by afirst etch and then transferred to the contact level dielectric layer510 by a second etch.

At operation 404, the method 400 (FIG. 4 ) deposits a diffusion barrierlayer 520 along exposed surfaces of the contact level dielectric layer510 followed by depositing a contact metal layer 530 over the diffusionbarrier layer 520. FIG. 5B is a cross-sectional view of thesemiconductor structure 500 after depositing the diffusion barrier layer520 along the exposed surfaces of the contact level dielectric layer 510followed by depositing the contact metal layer 530 over the diffusionbarrier layer 520.

Referring to FIG. 5A, the diffusion barrier layer 520 is deposited as asubstantially conformal layer covering the sidewalls and bottoms of thecontact openings 512, 514 and on the top surface of the contact leveldielectric layer 510. In some embodiments, the diffusion barrier layer520 includes a diffusion barrier material that prevents the metal in thecontact metal layer 530 from diffusing into the contact level dielectriclayer 510. In some embodiments, the diffusion barrier layer 520 includesTi, TiN, Ta, TaN, Ru, RuN, or other suitable diffusion barriermaterials. In some embodiments, the diffusion barrier layer 520 includesa stack of the above-mentioned diffusion barrier materials such as, forexample, Ti/TiN or Ta/TaN. In some embodiments, the diffusion barrierlayer 520 is deposited utilizing a conformal deposition process such asCVD, PECVD, PVD, or ALD. The diffusion barrier layer 520 is optional andmay be omitted in some embodiments.

The contact metal layer 530 is deposited on the diffusion barrier layer520, if present, to fill the contact openings 512, 514. In someembodiments, the contact metal layer 530 includes Cu, Al, W, Co, Ru, analloy thereof, or other suitable conductive metals. In some embodiments,the contact metal layer 530 is deposited using a suitable depositionprocess such as, for example, CVD, PECVD, sputtering, or plating. Thedeposition process is continued until the conductive material fills thecontact openings 512, 514 and extends above the contact level dielectriclayer 510. In some embodiments, when Cu or a Cu alloy is employed in thefirst metal layer, an optional plating seed layer (not shown) is formedon the second liner layer prior to the formation of the second metallayer. In some embodiments, the optional plating seed layer is formed bya deposition process including, for example, CVD, PECVD, ALD, and PVD.

At operation 406, the method 400 (FIG. 4 ) implants dopants into atleast a portion of the contact metal layer 530 in the small array region502S. In some embodiments, an entire portion of the contact metal layer530 in the small array region 502S is doped. FIG. 5C is across-sectional view of the semiconductor structure 500 of FIG. 5B afterimplanting the dopants into the entire portion of the contact metallayer 530 in the small array region 502S, in accordance with someembodiments. In some other embodiments, only an upper portion of thecontact metal layer 530 in the small array region 502S is doped. FIG. 5Dis a cross-sectional view of the semiconductor structure 500 of FIG. 5Bafter implanting the dopants into the upper portion of the contact metallayer 530 in the small array region 502S, in accordance with some otherembodiments.

Referring to FIGS. 5C and 5D, a patterned photoresist layer 540 isformed to mask a portion of the contact metal layer 530 in the largearray region 502L, while exposing a portion of the contact metal layer530 in the small array region 502S. In some embodiments, the patternedphotoresist layer 540 is formed by first applying a photoresist layerover the contact metal layer 530, exposing the photoresist layer toradiation through a photomask, and followed by etching away an exposedor unexposed region using a developer.

Subsequently, an ion implantation 550 is performed to introduce dopantsinto the portion of the contact metal layer 530 in the small arrayregion 502S that is exposed by the patterned photoresist layer 540,thereby forming a doped contact metal portion 530B in the contact metallayer 530. In some embodiments, the ion implantation 550 can beperformed by implanting dopant species including, but not limited to,carbon (C), silicon (Si), germanium (Ge) tin (Sn), a noble gas such ashelium (He), Neon (Ne), argon (Ar), krypton (Kr) or xenon (Xe), or amixture thereof, into the exposed portion of the contact metal layer530. Depending on the thickness of the contact metal layer 530 and thedopant species used, the implant dosage can range from 1×10¹²dopants/cm² to 5×10¹⁵ dopants/cm², and the implant energy can range from10 KeV to 150 KeV. One or more implant parameters such as implantdosage, implant energy and implant time may be adjusted to control thedepth of the ion implantation. In some embodiments, and as in FIG. 5C,the one or more implant parameters are controlled such that the contactmetal layer 530 in the small array region 502S is doped through itsentire thickness. That is, an entire portion of the contact metal layer530 within each second contact opening 514 in the small array region502S is doped. In alternative embodiments, and as in FIG. 5D, the one ormore implant parameters are controlled such that only an upper portionof the contact metal layer 530 in the small array region 202S is dopedwith dopants. That is, an upper portion of the contact metal layer 530within each second contact opening 514 in the small array region 502S isdoped. The undoped portion of the contact metal layer 530 is hereinreferred to as an undoped contact metal portion 530A. The introductionof dopants reduces the gain size of metal in the doped contact metalportion 530B. As a result, the grain size of metal in the doped contactmetal portion 530B is smaller than the grain size of metal in theundoped contact metal portion 530A. In some embodiments, the grain sizeof metal in the undoped contact metal portion 530A is in a range fromabout 0.5 μm to about 75 μRm, and the grain size of metal in the dopedcontact metal portion 530B is in a range from about 0.01 μm to about 0.5μm.

The ion implantation 550 also dopes at least a portion of the contactlevel dielectric layer 510 in the small array region 502S with dopants.In some embodiments, and as in FIG. 5C, an entire portion of the contactlevel dielectric layer 510 in the small array region 502S is doped. Inalternative embodiments, and as in FIG. 5D, only an upper portion of thecontact level dielectric layer 510 in the small array region 502S isdoped. The doped portion of the contact level dielectric layer 510 isherein referred to as a doped contact level dielectric portion 510B.

In some embodiments, after dopant species are implanted into the exposedportion of the contact metal layer 530 in the small array region 502S,the structure may be annealed. Such an anneal process can drive thedopants further into the contact metal layer 530 towards the substrate502. In some embodiments, the dopants in the doped contact metal portion530B may be uniformly distributed throughout its entire thickness. Insome embodiments, the dopants in the doped contact metal portion 530Bmay have a gradient dopant profile with the dopant concentration beingthe least at the bottom of the doped contact metal portion 530Bproximate to the substrate 502.

After the ion implantation, the patterned photoresist layer 540 isremoved by, for example, ashing.

At operation 408, the method 400 (FIG. 4 ) removes excess portions ofthe contact metal layer 530 and the diffusion barrier layer 520 outsidecontact openings 512, 514 to form a plurality of first contactstructures 560A in the large array region 502L and a plurality of secondcontact structures 560B in the small array region 502S. FIG. 5E is across-sectional view of the semiconductor structure 500 of FIG. 5C afterremoving the excess portions of the contact metal layer 530 and thediffusion barrier layer 520 outside the contact openings 512, 514 toform the plurality of first contact structures 560A in the large arrayregion 502L and the plurality of second contact structures 560B in thesmall array region 502S, in accordance with some embodiments. FIG. 5F isa cross-sectional view of the semiconductor structure 500 of FIG. 5Dafter removing the excess portions of the contact metal layer 530 andthe diffusion barrier layer 520 outside the contact openings 512, 514 toform the plurality of first contact structures 560A in the large arrayregion 502L and the plurality of second contact structures 560B in thesmall array region 502S, in accordance with alternative embodiments.

Referring to FIGS. 5E and 5F, the first contact structures 560A areformed in the large array region 502L of the substrate 502. Each of thefirst contact structures 560A includes a diffusion barrier 520P and afirst contact plug 562. The second contact structures 560B are formed inthe small array region 502S of the substrate 502. Each of the secondcontact structures 560B includes a diffusion barrier 520P and a secondcontact plug 564.

The first and second contact structures 560A, 560B can be formed by aplanarization process, such as CMP, which removes excess portions of thecontact metal layer 530 and the diffusion barrier layer 520 disposedover the top surface of the contact level dielectric layer 510. The CMPprocess may stop when reaching the contact level dielectric layer 510. Aremaining portion of the diffusion barrier layer 520 within each offirst and second contact openings 512, 514 constitutes the diffusionbarrier 520P. A remaining portion of the contact metal layer 530 withineach first contact opening 512 constitutes the first contact plug 562.The first contact plug 562 is formed with the undoped contact metalportion 530A. A remaining portion of the contact metal layer 530 withineach second contact opening 514 constitutes the second contact plug 564.At least a portion of the second contact plug 564 is made with a dopedcontact metal portion 530B. In instances where the entire portion of thecontact metal layer 530 in the small array region 502S is doped, afterthe planarization, an entirety of the second contact plug 564 is formedwith a doped contact metal portion 530B (FIG. 5E). In instances whereonly the upper portion of the contact metal layer 530 in the small arrayregion 502S is doped, after the planarization, the second contact plug564 has a bilayer structure including an undoped contact metal portion530A and a doped contact metal portion 530B overlying the undopedcontact metal portion 530A.

The CMP process exhibits a higher polishing rate for small grain sizemetal than large grain size metal. As a result, the doped contact metalportion 530B in the small array region 502S can be polished faster thanthe undoped contact metal portion 530A in the large array region 502L.Through control of local metal grain sizes which allows control ofpolishing rates in respective large array region 502L and small arrayregion 502S, the metal contact CMP loading effect is reduced, and theheight uniformity for contact structures 560A, 560B across the substrate502 is improved.

FIGS. 6A and 6B are cross-sectional views of a semiconductor structure600 that can be formed by performing the method 400 of FIG. 4 , inaccordance with some embodiments. Components in the semiconductorstructure 600 that are the same or similar to the semiconductorstructure 500 are given the same reference numbers, and detaileddescription thereof is thus omitted.

Unlike the semiconductor structure 500 in which the dopants are onlyimplanted into a portion of the contact metal layer 530 in the smallarray region 502S, in the semiconductor structure 600, dopants are alsointroduced into a portion of the contact metal layer 530 in theperipheral portion of the large array region 502L. As a result, thefirst contact structures 560A formed in the large array region 502Lincludes a pair of outer first contact structures 560A′ near the edgesof the series of the first contact structures 560 and inner firstcontact structures 560A″ between the outer first contact structures560A′. The first contact plug 562 in each of the outer first contactstructures 560A′ is formed with the doped contact metal portion 530B,while the first contact plug 562 in each of the inner first contactstructures 560A″ is formed with the undoped contact metal portion 530A.In some embodiments, and as in FIG. 6A, an entirety of the first contactplug 562 in each of the outer first contact structures 560A′ is formedwith the doped contact metal portion 530B. In some embodiments, and asin FIG. 6B, only an upper portion of the first contact plug 562 in eachof the outer first contact structures 560A′ is formed with the dopedcontact metal portion 530B. The first contact plug 562 in each of theouter first contact structures 560A′ thus has a bilayer structureincluding an undoped contact metal portion 530A and a doped contactmetal portion 530B atop of the undoped contact metal portion 530A.

During the CMP of the contact metal layer 530, selectively doping themetal in the portion of the contact metal layer 530 in the outer firstcontact structure region reduces the metal grains size, which leads toincrease in the metal removal rate in the outer first contact structureregion. As a result, the height uniformity of the resulting inner andouter first contact structures 560A′, 560A″ in the large array region502L is improved, which in turn leads to improved device performance.

One aspect of this description relates to a semiconductor structure. Thesemiconductor structure includes a substrate including a first activeregion in a first region of the substrate and a second active region ina second region of the substrate. A plurality of first gate structuresis over the first active region, each of the plurality of first gatestructures including a first gate stack comprising a first high-k gatedielectric and a first gate electrode and first gate spacers surroundingthe first gate stack. A plurality of second gate structures is over thesecond active region, each of the plurality of second gate structuresincluding a second gate stack comprising a second high-k gate dielectricand a second gate electrode and second gate spacers surrounding thesecond gate stack. At least a portion of the second gate electrodecomprises dopants.

Still another aspect of this description relates to a method of forminga semiconductor structure. The method includes forming a plurality offirst sacrificial gate structures over a first active region in a firstregion of a substrate and a plurality of second sacrificial gatestructures over a second active region in a second region of thesubstrate. Each of the plurality of first sacrificial gate structuresand the plurality of second sacrificial gate structures includes asacrificial gate conductor and gate spacers surrounding the sacrificialgate conductor. After depositing a dielectric layer over the substrateto surround the plurality of the first sacrificial gate structures andthe plurality of second sacrificial gate structures, the sacrificialgate conductor from each of the plurality of first sacrificial gatestructures and the plurality of second sacrificial gate structures isremoved to provide a plurality of first gate cavities in the firstregion and a plurality of second gate cavities in the second region. Ahigh-k dielectric layer is then deposited along sidewalls and bottoms ofthe plurality of first gate cavities and the plurality of second gatecavities and over a top surface of the dielectric layer, followed bydepositing a gate electrode layer over the high-k dielectric layer tofill the plurality of first gate cavities and the plurality of secondgate cavities. Next, dopants are implanted into a portion of the gateelectrode layer in the second region of the substrate, while maskinganother portion of the gate electrode layer in the first region of thesubstrate. Subsequently, excess portions of the gate electrode layer andthe high-k dielectric layer are removed from the top surface of thedielectric layer.

Still another aspect of this description relates to a semiconductorstructure. The semiconductor structure includes a dielectric layer overa substrate including a first region and a second region. A plurality offirst contact structures is in a portion of the dielectric layer in thefirst region of the substrate, each of the plurality of first contactstructure including a first contact plug. A plurality of second contactstructures is in another portion of the dielectric layer in the secondregion of the substrate, each of the plurality of second contactstructure including a second contact plug. The first contact plugincludes a metal of a first grain size and at least a portion of thesecond contact including the metal of a second grain size less than thefirst grain size.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure. cm What is claimed is:

1. A method of forming a semiconductor structure, comprising: forming aplurality of first sacrificial gate structures over a first activeregion in a first region of a substrate and a plurality of secondsacrificial gate structures over a second active region in a secondregion of the substrate, each of the plurality of first sacrificial gatestructures and the plurality of second sacrificial gate structurescomprises a sacrificial gate conductor and gate spacers surrounding thesacrificial gate conductor; depositing a dielectric layer over thesubstrate to surround the plurality of the first sacrificial gatestructures and the plurality of second sacrificial gate structures;removing the sacrificial gate conductor from each of the plurality offirst sacrificial gate structures and the plurality of secondsacrificial gate structures to provide a plurality of first gatecavities in the first region and a plurality of second gate cavities inthe second region; depositing a high-k dielectric layer along sidewallsand bottoms of the plurality of first gate cavities and the plurality ofsecond gate cavities and over a top surface of the dielectric layer;depositing a gate electrode layer over the high-k dielectric layer tofill the plurality of first gate cavities and the plurality of secondgate cavities; implanting dopants into a portion of the gate electrodelayer in the second region of the substrate, while masking anotherportion of the gate electrode layer in the first region of thesubstrate; and removing excess portions of the gate electrode layer andthe high-k dielectric layer from the top surface of the dielectriclayer.
 2. The method of claim 1, wherein implanting the dopantscomprises implanting the dopants into the portion of the gate electrodelayer in the second region of the substrate through an entire thicknessof the gate electrode layer.
 3. The method of claim 1, whereinimplanting the dopants comprises implanting the dopants into an upperportion of the portion of the gate electrode layer in the second regionof the substrate.
 4. The method of claim 1, wherein the dopants comprisecarbon, silicon, germanium, tin, helium, Neon, argon, krypton, xenon ora mixture thereof.
 5. The method of claim 1, the excess portions of thegate electrode layer and the high-k dielectric layer from the topsurface of the dielectric layer are removed by a chemical mechanicalpolishing process.
 6. The method of claim 1, further comprising formingfirst source/drain structures on opposite sides of the plurality offirst sacrificial gate structures and second source/drain structures onopposite sides of the plurality of second sacrificial gate structures.7. A semiconductor structure, comprising: a dielectric layer over asubstrate comprising a first region and a second region; a plurality offirst contact structures in a portion of the dielectric layer in thefirst region of the substrate, each of the plurality of first contactstructure comprising a first contact plug; and a plurality of secondcontact structures in another portion of the dielectric layer in thesecond region of the substrate, each of the plurality of second contactstructure comprising a second contact plug, wherein the first contactplug comprises a metal of a first grain size and at least a portion ofthe second contact comprises the metal of a second grain size less thanthe first grain size.
 8. The semiconductor structure of claim 7, whereinthe first contact plug is free of the dopants.
 9. The semiconductorstructure of claim 7, wherein the at least the portion of the secondcontact plug comprises dopants.